Abstract: The paper discusses the application of VLSI technology to implement the functions of multi operand floating point addition in parallel using verilog, targeting it to a Xilinx FPGA. The multi operand floating point adders perform two additions in a single unit to achieve better performance and accuracy. To improve the performance and accuracy, several optimization techniques are applied. These are a new exponent compare and significant alignment, dual-reduction, early normalization, three input leading zero anticipation and compound addition and rounding. The traditional fused floating point three term adder takes twice the area, power consumption and delay. In order to reduce the overhead the multi-operand floating point adder has been proposed. Which perform rounding only once, which improve the accuracy.

Keywords: Xilinx FPGA, adders, zero anticipation, multi-operand floating point adder.