Abstract: Multipliers are essential component of digital signal processing as they are used for determining the speed of Digital Signal Processor (DSP). The floating point complex multiplication is one of the basic functions used in digital signal processing application, microprocessors and FIR filters. Floating point format is a standard format used almost in all processing elements. Delay and power are main parameters used to determine the speed of multiplier. Conventional multipliers require more delay and hence consume more power for the multiplication. The Vedic mathematics technique is widely used because of its fast computational ability. This paper presents a review of 32bit single precision floating point complex multiplier using Vedic mathematics and proposes a design for high speed 32 bit single precision floating point complex multiplier using Vedic mathematic.
Keywords: Digital Signal Processor (DSP), Vedic mathematics, complex multiplier, floating point number.