Abstract: Full adder circuit is a very important component in the design of application of integrated circuits in VLSI. This paper explores the design and analysis of four different 1 bit Full Adder cell using the Modified Gate Diffusion Input (MGDI) technique on optimizing the power, delay and Power Delay Product (PDP). This technique (MGDI) allows reducing power, delay and area of digital circuits, while maintaining low complexity of logic design. Through investigation is carried out for the effectiveness using combination of different low power full adder circuit design techniques. The main objective of these full adders is providing high-speed and low power consumption also provides good voltage swing. This can be achieved by applying the low power techniques for reduction of power and delay. This work presents comparison of the different low power full adder cell on the power dissipation, delay and Power delay product. The full adder design simulations are implemented using 90nm technology with Tanner EDA Tool.

Keywords: Full Adder, GDI, MGDI, Power, Delay, PDP.