Abstract: One of the most important analog circuits required in many analog integrated circuits is comparator. It is used for the comparison between two same or different electrical signals. The Comparator design becomes an important issue when design technology is scaled down. Due to the non-linear behavior of threshold voltage (Vt) when design technology is scaled down, performance of Comparator is most affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron design technologies. The selection of particular topology is dependent upon the requirements and applications of the design. Low power circuit design has emerged as a principal theme in today’s electronics industry. In this project comparator architecture their design parameter, study about offset voltage and sources of power and their estimation and reduction technique are discussed. The need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this project, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation will be carried out in 180nm CMOS technology using Cadence 6.1.5 version.

Keywords: ADC (Analog to Digital Converter), CMOS (Complementary Metal Oxide Semiconductor), dynamic comparators, Cadence Virtuoso.