Abstract: Divider is a basic hardware module in advanced and high speed digital signal processing (DSP) units. It has the applications in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper presents 4-bit Serial Divider using Modified GDI Technique. The repeated one’s complement method of binary subtraction algorithm is used for serial division. The proposed method aims on Modified Gate Diffusion Input (mod-GDI) which is a low power technique to design any digital system. This technique has been adopted from Gate Diffusion Input (GDI).The Modified GDI technique which allows in reducing delay, power consumption and area compared to conventional CMOS Technology. According to the estimations done, the transistor count, Tool analysis time, power consumption of serial divider using CMOS technology and the Modified GDI technique is tabulated. The designs are simulated using the Tanner EDA tool.

Keywords: GDI, Modified-GDI, Transistor Count, Power Consumption, One’s Complement Method of Subtraction.