Abstract: An advanced approach to design a fault coverage test pattern generator by utilizing linear feedback shift register called Bit Swap-LFSR. This could perform fault analysis and also minimize the power utilization at circuit level during tests, by generating three intermediate patterns between random patterns by decreasing the hardware components usage. The main purpose of having intermediate patterns is to minimize the transitional processing at initial inputs; this could minimize the switching activities at circuit under test. By this the power consumption is decreased without any lose or damage in the hardware components. This experiment results by efficient multipliers circuits in proposed system, with and without fault confirm of fault coverage when the circuit has been tested.
Keywords: LFSR, Low Power Test Pattern Generation, BIST, ATE.