Abstract:
Any Integrated circuit (IC) manufactured by the semiconductor manufacturing company contains test circuit and the circuit under test (CUT). The test circuit is used to test the correct functionality of the CUT and which is called Built In Self Test (BIST). This Built In Self Test used to generate test vectors which are applied to the circuit under test by inbuilt chip within an integrated circuit. In pseudorandom BIST design, the test vectors are generated in random style by Linear Feedback Shift Registers (LFSR). The main drawback of these conventional LFSRs is, it generates normally a number of random natured test vectors for testing the CUT in which many are repeated vectors and application of which unnecessarily increase the test power without contributing much to the fault coverage also the bulkiness of the CUT increases. This paper presents a new approach, called Low Power -Bit complement test vector generation technique (LP-BCTVG). In LP-BCTVG technique, the output bits are complemented due to which unreported test vectors are increasing also by which better fault coverage with a reduction in the bulkiness of the test circuit can be achieved.

Keywords: Low power- Bit complement Test vector Generation (LP- BCVPG), Bulkiness, test power and Linear feedback shift register (LFSR)