Abstract:
The Finite Impulse Response digital filter is widely used as a basic tool in various signal time realization of FIR ( Finite Impulse Response filter) with less hardware requirement and less latency has become more and more important. The design method of MAC (multiplication and accumulation) operation is the core of FIR filter implementation. Distributed Arithmetic is an important technique to implement digital signal processing (DSP) functions in FPGA (Field Programmable Gate Arrays). It provides an approach for multiplier-less implementation of FIR filter, since it is an algorithm that can perform multiplication with use of LUT (look Up Table) that stores the pre-computed values and can be read out easily which makes DA (Distributed Arithmetic)based computation well suited for FPGA realization, because the LUT is the basic component of FPGA. The major disadvantage of DA technique is that the size of Da-LUT increased exponentially with the increasing length of input. Several efforts have been made to reduce the Da-LUT size for efficient realization of DA-based designs. In this paper, LUT is partitioned into smaller size LUT, so that the LUT size can be reduce to one fourth (the size of the table is reduced from one 4N*2B LUT to four N*2B tables). Hence the length of the LUT can be reduced.

Keywords: Distributed Arithmetic, Finite Impulse Response, Look Up Table