Abstract:
Area and power are the two vital issues in analog circuit design and synthesis of ULSI and VLSI circuits which depends on various critical design parameters. The purpose of this paper is the design and implementation of an Arithmetic Logic Unit (ALU) using area optimizing techniques such as complementary & Gate-Diffusion-input (GDI). The main sub-blocks of ALU are Adder, Subtractor, shifter and Logical Block. This work evaluates and compares the performance and optimized area of ALU with Static CMOS technique and GDI technique in 250nm CMOS (1P5M-1 Poly 5 Metal) process technology. Simulations are performed by using Tanner EDA 13.2 tools using model file 250nm CMOS technology. At first, using Tanner 13.2 EDA S-Edit Tool, the circuits are implemented with Static CMOS technology and then with GDI techniques. Simulations results validate the proposed concept and verify that GDI technique decreases the area used by ALU and increase the speed of ALU.

Keywords: ALU, VLSI, GDI, CMOS, Low Power, Power Dissipation, Optimized ALU