Abstract:
The 8255A programmable peripheral interface PPI) implements a general-purpose I/O interface to connect peripheral equipment to a microcomputer system bus. The core’s functional configuration is designed by VHDL code and designed input signal (Test bench) for PPI 8255, which is generated by VHDL code. Simulated result is verified for one 8-bit Peripheral Ports - Ports A, three programming modes for Peripheral Ports: Mode 0 (Basic Input/output programmable I/O lines .Also verified simulated and synthesized result for PPI 8255. All designed is done by using Xilinx ISE10.1i.

Keywords: VHDL Code, MOS, MCS85, PPII