Abstract:
Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms in different compression methods applications. In a distributed environment, large data files remain a major bottleneck. Compression is an important component of the solutions available for creating file sizes of manageable and transmittable dimensions. When high-speed media or channels are used, high-speed data compression is desired. Software implementations are often not fast enough. In this paper, we present the very high speed hardware description language (VHDL) modeling environment of Lempel-Ziv-Welch (LZW) algorithm for binary data compression to ease the description, verification, simulation and hardware realization. The LZW algorithm for binary data compression comprises of two modules compressor and decompressor. The input of compressor is 1-bit bit stream read in according to the clock cycle. The output is an 8-bit integer stream fed into the decompressor, which is an index that represents the memory location of the bit string stored in the dictionary. In this paper, data compression technique is described using Lempel-Ziv-Welch algorithm. Software reference model for data compression using LZW has been modelled in MATLAB/ Simulink.

Keywords: Binary Data Compression, LZW, Lossless data compression, VHDL Simulation