Abstract:
By using viterbi decoder the power can be reduced according to number of stages used in each block. The efficient way to reduce data corruption in digital communication channels using various decoding algorithm. Although hardware implementations of decoding algorithms, (i.e.,) Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these hardware implementations require an exponential increase in VLSI area and power consumption to achieve increased decoding accuracy in different stages. To achieve reduced decoder power consumption, we noticed the hardware implementation decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). In proposed decoding method the overall power reduced in each module can be improved when compared to previous method.