Abstract: An improved and power efficient layout is proposed for Conventional TSPC prescaler and Design-I ofbase paper and compared with the existing TSPC and E-TSPC prescalers on the basis of operating frequency and power consumption. The proposed layout of Conventional TSPC prescaler can operate up to 5.1 GHz with 264 W power consumption at 1.8 V supply voltage for both divide by 2 and divide by 3 mode, which is three times power efficient with 20% improved frequency response. The lowest power consumption is achievedin improved layout of Design-I ofbase paper based architecture which can operate up to 6GHz and consumes 290 W power for divide by 2 mode and 199 W for divide by 3 mode at 1.8V supply voltage, which is two and half times power efficient with 10% better frequency response.

Keywords: Dual modulus prescaler, D Flip-flop (DFF), True single phase clock (TSPC), Microwind, DSCH, Frequency synthesizer, Clock, Propagation Delay.