Abstract: An efficient adaptive filter architecture using booth multiplier has been developed. For deriving low-complexity and high-speed implementation a precise analysis of the critical path of the least-mean-square (LMS) adaptive filter has been done in this paper. For achieving area-delay-power efficient implementation and lower adaptation-delay, we use efficient partial product generator and propose a method for optimization of the time-consuming combinational blocks of the structure by using pipeline stages. We proposed an area-delay-power efficient lower adaptation delay architecture for implementation of LMS adaptive filter. We used partial product generator for efficient implementation of bitwise multiplications and inner-product computation by sharing the common sub expressions. In multiplier major part of the delay is contributed by partial product addition. In order to reduce the delay Carry look ahead adder is used as the adder to perform partial product addition in the adder tree. The propagation delay occurred in the parallel adders can be eliminated by carry look ahead adder. The proposed structures involves significantly less adaptation delay and provide significant saving of ADP compared to the existing structures. We use Xilinx 14.7 to provide VHDL coding for our architecture. Result shows that proposed structure has better performance than existing algorithms.
Keywords: Adaptive filter, Least Mean Square, Carry Look Ahead Adder, Booth Multiplier.