Abstract: Computerized Signal Processors (DSPs) and application particular coordinated circuits depend on the proficient usage of math circuits to execute committed calculations, for example, convolution, connection and separating. The general execution of these frameworks relies on upon the throughput of the multiplier. This paper exhibits a near examination of three distinctive multiplier structures. The three multipliers design are exhibit multiplier, a section sidestep multiplier, and a cluster multiplier utilizing Reversal Logic plans. The multipliers are executed on Spartan 6 FPGA. The structures are thought about as far as basic way defer, power dissemination and range. The distinctive multipliers are looked at as far as dynamic force utilization because of the scaling impacts on spillage current. Each of the three multipliers has its own exchange offs in the middle of force and postpone.
Keywords: Low Power, Multiplier, Switching Delay, bypassing techniques, reversible logic.