Abstract: Power utilization is a main sympathy toward all VLSI circuits architects. Arithmetic operations is done by multiplexer as far as shift and add operation. A Wallace tree multiplier is a rapid speed multiplier utilize full and half adder in the reduction stage. By outlining the reduced complexity Wallace multiplier to conventional Wallace multiplier the number MOS transistor is less. in the proposed method as far as area and power estimation of XOR-XNOR gates and MUX blocks discovered effective. The proposed phase of Wallace multiplier is performed with less area, power, and delay.
Keywords: Wallace tree multiplier, Multiplexer, Full adder, SAED90nm.