Abstract: In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported and it is incorporated in a 2-bit comparator design. The circuit was implemented using Tanner tools. Performance parameters such as power, delay, and layout area were compared with the existing designs such as classical CMOS full adder(C-CMOS),complementary pass-transistor logic(CPL), transmission gate adder(TGA) and so on. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed and thus in a 2-bit comparator design.
Keywords: Carry propagation adder, hybrid design, low power, CMOS (Complementary Metal Oxide Semiconductor), high speed, Tanner tool.