Abstract: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. A parallel prefix adder involves the execution of the operation in parallel which can be obtained by segmentation into smaller pieces. The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including Arithmetic and Logic Unit (ALU), microprocessors and Digital Signal Processing (DSP). At present, the research continues on increasing the adder’s delay performance.In this paper the investigation of four types of PPA’s (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)) is done. Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.4 Design Suite. The area, delay and power consumed by all types of PPA’s are analyzed. The area of the adder design are given in terms of Look Up Tables (LUT’s) and Input Output bounds (IOB’s). The adder designs are implemented and delay, power and area of all the adders are investigated.
Keywords: PPA, RCA, CLA, SKA, KSA, BKA, STAFPGA, Delay, Power, Area