Abstract: In network infrastructure packet classification is a core function for various applications which is widely used. Performing wire speed classification is becoming a challenge because of demand in increasing throughput. Performance of packet classification these days depends on rulesets and its characteristics. A high speed packet classification based on Bit-Vector (BV) based architecture implemented on FPGA (Field Programmable Gate Array) is proposed. StrideBV is the algorithm introduced and BV architecture is modularized to achieve better scalability than BV traditional methods. The solution introduced here is ruleset-feature independent, the performance is mostly guaranteed for any ruleset regardless the ruleset and its composition. The proposed design is implemented in SPARTAN3 or higher devices FPGA by using Xilinx ISE 13.4 and simulated in modelsim 6.3f. The Chipscope pro Analyzer is used to view the execution results of FPGA.
Keywords: classification, firewall, router, network security, FPGA, networking.