Abstract: In this paper, a high performance pulse Triggered flip- flop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. This enhanced pulse triggered low-power flip flop (EPTLFF) avoids unnecessary internal node transitions to improve the power consumption as compared to previously designed circuits. A 4-bit counter is also designed using proposed EPTL. This design features the reduced power consumption and power-delay-product performance as compared to the other two types of flip flops which are implemented. These designs are simulated using mentor graphics schematic editor tool.
Keywords: Flip-flop, low power, pulse-triggered.