**Abstract:**
Residual Number System (RNS) represents a larger integer using a set of smaller integer for a set of selected moduli [1]. The computation part of the RNS has an integer part multiplied with the selected modulo and a residual part. The selected moduli are absolute values, which are relatively prime [1][2]. In RNS multiplication process the residues of the multiplier and multiplicand are obtained for set of moduli and multiplied respectively to get the residues of final product. The conversion of RNS to Decimal Number System is done by Chinese Remainder Theorem (CRT).In RNS multiplication process, multiplication of large numbers can be done at the same speed as on short numbers. The speed is determined by the largest modulo position. The computation complexity is decreased by representing the larger number as set of smaller numbers. In this project, a comparison will be carried out between the Booth multiplier, Modified Booth multiplier and Radix-8 Booth multiplier with and without using RNS and are designed using Verilog HDL and implemented in FPGA. These multipliers are checked for Power and Efficiency.

**Keywords:**
RNS (Residual Number System), CRT (Chinese Remainder Theorem).