Abstract: : Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for cost effective data converters that will achieve higher speed and resolution. Comparator is one of the main building blocks in most analog-to-digital converters. Many high speed analog to-digital converters, such as flash ADCs, require high-speed, low power comparators with small chip area. In low power, area efficient, and high speed analog-to-digital converters we need dynamic regenerative comparators to increase speed and power efficiency. In this paper, a new dynamic comparator is proposed, where the circuit of a low voltage low power double tail comparator is modified for area efficient and double edge triggered operation. This paper provides a comprehensive review about a variety of comparator designs - in terms of performance, power and delay using Cadence Virtuoso CMOS 180-nm technology.
Keywords: ADC (Analog to Digital Converter), CMOS (Complementary Metal Oxide Semiconductor), dynamic comparators, Cadence Virtuoso.