Abstract: As design systems have grown in complexity and clock speeds are constantly increasing, several limitations to the conceptual framework of synchronous design have begun to be noticed. Some notable problems due to higher performance demand are difficulty in global distribution of clock, clock skew, high power dissipation, interfacing difficulties and traversing the chipís longest wire in one clock cycle. It is therefore not a surprise that the area of asynchronous circuits and systems, which generally do not suffer from these problems are gaining importance. Here we take into account new research concept which improves digital system implementations, which is basically asynchronous digital design. Asynchronous systems can be realized using clock-less chip implementation techniques which avoids the clock. This system gives importance to the arrival of data and sequence, only when required, thus reducing power consumption, EMI etc. The proposed methodology ensures the validity of the data by taking care of glitches, delays and hazards. The design of a new methodology for asynchronous system development is discussed in this paper.

Keywords: VLSI, Clock-less system, hazard, Asynchronous design, skew, data completion, Threshold gate, NCL.